A flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) device includes an array of cells that can be independently programmed and read. The size of each cell and thereby the memory device are made small by omitting transistors known as select transistors that enable the cells to be erased independently. As a result, a group of the cells must be erased together as a block.
A flash memory device of this type includes individual Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) memory cells, each of which includes a source, a drain, a floating gate and a control gate to which various voltages are applied to thereby program the cell with a binary 1 or 0, to erase all or some of the cells as a block, to read the cell, to verify that the cell is erased or to verify that the cell is not over-erased.
Memory cells in a flash memory device are typically connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective word line and the drains of the cells in a column being connected to a respective bit line. The sources of all the cells may be connected together.
A cell is typically programmed by applying a voltage to the control gate, applying a voltage to the drain and grounding the source. A cell is typically read by applying a voltage to the word line to which the control gate of the cell is connected, applying a voltage to the bit line to which the drain of the cell is connected, grounding the source, and sensing the bit line current. If the cell is programmed and the threshold voltage is relatively high, the bit line current will be zero or nearly zero. If the cell is not programmed or erased, the threshold voltage will be relatively low, the control gate voltage will enhance the channel, and the bit line current will be relatively high.
A cell can be erased in several ways. In one arrangement, a cell may be erased by applying a relatively high voltage to the source, grounding the control gate and allowing the drain to float. These applied voltages cause the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. In another arrangement, applying a negative voltage to the control gate, applying a voltage to the source and allowing the drain to float also erases a cell. A further method of erasing a cell is accomplished by applying a voltage to the P-well (substrate) and a negative voltage to the control gate, while allowing the source/drain to float.
A problem with the conventional flash EEPROM cell arrangement is that due to manufacturing tolerances, some cells become over-erased before other cells are sufficiently erased. The floating gates of the over-erased cells are depleted of electrons and become positively charged. The over-erased cells then effectively function as depletion mode transistors that cannot be turned off by applying normal operating voltages to their control gates. The cells functioning as depletion mode transistors also introduce leakage current during subsequent program and read operations.
More specifically, during program and read operations only one word line connected to the control gates of a row of cells is held high at a time, while the other word lines are grounded. A positive voltage is applied to the drains of all of the cells and if the threshold voltage of an unselected cell is zero or negative, the leakage current will flow through the source, channel and drain of the cell.
The undesirable effect of the leakage current from the over-erased cells is as follows. In a typical flash EEPROM, the drains of a large number of memory transistor cells, for example 512 transistor cells are connected to each bit line. If a substantial number of cells on the bit line are drawing background leakage current, the total leakage current on the bit line can exceed the cell read current. This makes it impossible to read the state of any cell on the bit line and therefore renders the memory inoperative.
Because the background leakage current of a cell varies as a function of threshold voltage, the lower (more negative) the threshold voltage the higher the leakage current. It is therefore desirable to prevent cells from being over-erased by reducing the threshold voltage distribution to as low a range as possible, with ideally all cells having the same threshold voltage after erase.
It is known in the art to reduce the threshold voltage distribution by performing an over-erase correction operation, which reprograms the most over-erased cells to a higher threshold voltage. An over-erase correction operation of this type is generally known as Automatic Programming Disturb after Erase (APDE).
One APDE method includes sensing for over-erased cells and applying programming pulses thereto, which bring their threshold voltages back to acceptable values. Following application of an erase pulse, under-erase correction may be performed on a cell-by-cell basis by row. The cell in the first row and column position may be addressed and erase verified by applying a voltage to the control gate (word line), a voltage to the drain (bit line), grounding the source, and using sense amplifiers to sense the bit line current to determine if the threshold voltage of the cell is above a value of, for example, 2 volts. If the cell is under-erased, indicated by a threshold voltage above 2 volts, the bit line current will be low. In this case, an erase pulse (e.g., a bias voltage) is applied to all of the cells, and the first cell is erase verified again.
After application of each erase pulse and prior to a subsequent erase verify operation, over-erase correction may be performed on all the cells in the memory. Over-erase verification may be performed on the bit lines of the array or memory in sequence by grounding the word lines, applying a voltage to each bit line in sequence and sensing the bit line current. If the bit line current is above a predetermined value, at least one of the cells connected to the bit line is over-erased and is drawing leakage current. In this case, an over-erase correction pulse is applied to the bit line. The over-erase correction pulse may be applied to the bit line for a predetermined length of time, typically 100 μs.
After application of the over-erase correction pulse to the bit line, the cells on the bit line are over-erase verified again. If the bit line current is still high indicating that an over-erased cell still remains connected to the bit line, another over-erase correction pulse is applied to the bit line. This procedure is repeated, as many times as necessary until the bit line current is reduced to the predetermined value that is lower than the read current. Then, the procedure is performed for the rest of the cells in the first row and following rows until all of the cells in the memory have been erase verified.
By performing the over-erase correction procedure after each erase pulse, the extent to which cells are over-erased is reduced, improving the endurance of cells. Further, because over-erased cells are corrected after each erase pulse, bit line leakage current is reduced during erase verify, thus eliminating under-erased cells upon completion of the erase verify procedure.
Over-erase correction pulses, as described above, may be applied to each column of connected memory cells for a predetermined time period to inject a particular amount of charge carriers, such as electrons, into the floating gate structure of each flash memory cell to raise the threshold voltage of each flash memory cell. The longer the time period for applying such a pulse, the higher the increase in the threshold voltage of each flash memory cell. The higher the threshold voltage of each flash memory cell, the lower the leakage current through each flash memory cell. Such a time period for applying the pulse for the APDE process may be referred to as the “APD” time.
Unfortunately, it has been found that the length of the APD time period for each of the flash memory cells attaining the desired threshold voltage is affected by the leakage current of the other commonly connected flash memory cells. When this leakage current flows through resistors coupled at the drain of the flash memory cells, the resulting voltage across the drain and source terminals of the flash memory cells is lowered. Such lowered voltage across the drain and source terminals decreases the rate of charge carrier injection into the floating gate structure of the flash memory cells for a less efficient APDE process.
The level of leakage current is especially acute for flash memory cells having scaled down dimensions of hundreds of nanometers for the channel length because of DIBL (Drain Induced Barrier Lowering). For example, when the channel length of each flash memory cell is less than about 0.22 μm, the DIBL voltage change at the drain of a flash memory may be greater than about 0.6 Volts. Despite higher leakage current with a smaller flash memory cell, the dimensions of the flash memory cell are desired to be scaled down further for enhanced speed performance and smaller occupied area.
Applying the over-erase correction pulses of the APDE process for a longer period of time (i.e., a higher APD time) ensures a higher average threshold voltage for the column of flash memory cells to minimize leakage current. A predetermined APD time is used for each cycle in the APDE process such that an acceptably low level of leakage current flows through the column of flash memory cells. However, a higher APD time disadvantageously slows down the erasing cycle of the flash memory array.